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3 comments:

  1. Dave Taht 26 January 2018 20:34
    Sigh. To me it's not the size of the buffer but how it is managed - aqm and fq would help big buffered switches also - fq speeding up small transactions in particular.
  2. Blake 26 January 2018 20:43
    Realistically, I think boxes with *intelligent* small buffers make the most sense. "Large buffer" is relative w/6tbps+ ASICs...

    We want CAKE (or at least fq-codel) in silicon.
    & if you haven't seen Mark Handley's NDP demo video, it'll blow your mind:
    https://www.youtube.com/watch?v=BO0QhaxBRr0
    Replies
    1. Ivan Pepelnjak 27 January 2018 08:42
      Awesome concept ;) So glad to see at least some people are thinking outside of the usual box.

      Do have to mention though that the idea of clearing CLP bit on the last ATM cell in an AAL5 frame once you start dropping the cells due to congestion is a bit like trimming the packet down to its header ;)
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